A high frequency power amplification unit employed for such a radio communication device as a car telephone, mobile phone, or the like is configured by a plurality of amplifiers, each being configured by a transistor (semiconductor amplification element) and connected to another serially. Usually, two or three of such amplifiers are disposed in a plurality of amplification stages. The amplifier in the last stage (final amplification stage) is defined as an output one and each amplifier (amplification stage) positioned before the final amplification stage is defined as a driving stage. An inductor used to adjust the circuit impedance is built in each of those amplification stages.
This type of high frequency power amplification is already disclosed in the official gazettes of Japanese Unexamined Patent Publication No. Hei 9(1997)-283700 and Japanese Unexamined Patent Publication No. Hei 10(1998)-70159. In the high frequency power amplifier disclosed in the official gazette of Japanese Unexamined Patent Publication No. Hei 9(1997)-283700, a power transistor (semiconductor chip: bare chip) is fixed at the bottom of each aperture provided in the top face of a multi-layer substrate formed mainly of glass. A gap is formed between the periphery of the power transistor and the inner wall surface of the aperture. Consequently, the fixing position of the power transistor (semiconductor chip) is never restricted by the inner wall of the aperture.
The official gazette of Japanese Unexamined Patent Publication No. Hei 10(1998)-70159 describes a technique for manufacturing a high frequency module in which a semiconductor chip is provided at the bottom of each aperture provided in the main surface of a printed circuit board. Also in this example, the semiconductor chip never comes in contact with the inner wall of the aperture, so that its fixing position is not restricted by the inner wall of the aperture.
On the other hand, the official gazettes of Japanese Unexamined Patent Publication No. Hei 5(1993)-13474 and Japanese Unexamined Patent Publication No. Hei 9(1997)-148623 disclose techniques for fixing a semiconductor chip in a predetermined position respectively.
According to the technique disclosed by the official gazette of Japanese Unexamined Patent Publication No. Hei 5(1993)-13474, an area on a die pad is plated in a similar shape to that of a die to be mounted on the die pad or a size smaller than the die, then the die is placed on the plated die pad together with a wax material, and finally adhered with the wax material there accurately.
The official gazette of Japanese Unexamined Patent Publication No. Hei 9(1997)-148623 discloses a technique for fixing a light receiving/emitting element on the target substrate. According to the technique, a laminated metallic layer of the same in size as the light receiving/emitting element is provided on the target substrate beforehand, then the element is heated to improve the accuracy of the height between the reference plane and the light axis of the light receiving/emitting element, thereby the light receiving/emitting element is fixed accurately there.
The official gazette of Japanese Unexamined Patent Publication No. Hei 5(1993)-114800 also discloses a technique for fixing a semiconductor chip accurately in a rectangular recess formed in the target substrate. According to the technique, fine vibrations are applied to the recess by supersonic waves to position and fix the semiconductor chip accurately. However, this technique just positions and fixes the semiconductor chip in the recess by inclining the inner wall of the recess and using the inclined plane to move the chip or using a surface tension of a member having the predetermined surface tension, which is inserted between the chip and the side face (inner wall) of the recess. It does not restrict the fixing position of the semiconductor chip directly by the inner wall of the recess.
As described above, the high frequency power amplification unit is used as an amplifier of the subject mobile phone. A high frequency power amplification unit (high frequency power amplification module) built in a mobile phone usually employs a multistage structure in which two or three transistors (semiconductor amplification elements) are connected serially to form a multistage amplifier unit. The electrode of each transistor is connected to such a wiring line as a micro-strip line of the module substrate through a conductive wire.
Generally, a chip bonding device is used to supply semiconductor chips to be fixed in the manufacturing process of the high frequency power amplification module. The accuracy of positioning and fixing those chips is decided by the performance accuracy of the chip bonding device or the solder reflowing after the chip is supplied.
In any way, the accuracy of positioning and fixing semiconductor chips comes to be affected by the supplying accuracy of those chips by a chip bonding device or the like.
If the fixing position of a semiconductor chip is varied, the length of the wire for connecting the electrode provided on the surface of the semiconductor chip to a wire electrically in the subsequent process comes to be varied.
Conventionally, consideration has been taken only to the accuracy in chip bonding of each transistor (semiconductor chip) of the high frequency power amplification module in its predetermined position. And, it has been considered that if a semiconductor chip is fixed accurately, the wire length also comes to be determined as it is designed.
In such a radio communication device as a mobile phone that is required of high and efficient outputs, however, such conventional techniques have been found imperfect, since the techniques depend only on the performance of such a chip bonding device. In other words, it is found that in a high frequency power amplification module that employs a multistage amplifier unit, if the connection length between the output terminal of the transistor in the final amplification stage (for example, drain electrode of an FET and collector electrode of a bipolar transistor) and a wiring is varied, the parasitic inductance comes to be varied and both output and efficiency of the device come to be varied.
To avoid such a problem, therefore, it is desirable that the length of the wire for connecting the output terminal of the transistor in the final stage to a wiring should be shorter to reduce the parasitic inductance.
FIG. 25 shows a typical cross sectional view of a wire bonding portion according to a conventional technique, which includes a problem that must be solved. As shown in FIG. 25, in a ceramic wiring board 70 manufactured by a lamination method, the periphery of a recess 71 formed in a main surface (top face) of the board 70 is shaped as an inclined or arc plane due to the sags that occur at the manufacturing time, thereby the surface of each bonding pad used to connect a wire also comes to be shaped as an inclined or arc plane. As a result, the connection property of the wire bonding is often degraded.
In other words, the ceramic wiring board 70 is formed as follows; at first, a plurality of patterned green sheets that include a printed conductor layer are laid in layers and pressed into a laminated substrate, then the laminated substrate is heated and baked to obtain a baked ceramic plate to be used as the board 70. In this baking process, the periphery of the recess 71 is melted and flown into the recess. This is why the periphery of the recess 71 comes to sag.
If a bonding pad for wire bonding is formed at a halfway to the periphery of the recess 71, therefore, the top face of the bonding pad is not flattened, but inclined or arced, resulting in imperfect wire bonding.
To avoid such problems, the inventors of the present invention propose a technique for disposing a bonding pad 72 outside a position apart from the periphery of the recess 71 by a predetermined distance “a”. This bonding pad 72 is connected to one end of the wire 76 having the other end connected to the electrode 75 of the semiconductor element (semiconductor chip) 74 fixed at the bottom of the recess 71 with a bonding material (fusion boding material) 73 therebetween. The bonding pad 72 is also connected to the wiring 77.
In such a structure, however, the wire 76 for connecting the electrode 75 of the semiconductor element (semiconductor chip) 74 to the bonding pad 72 comes to be longer, thereby the parasitic inductance increases.
Under such circumstances, it is an object of the present invention to accurately position and fix a semiconductor element in an amplification stage of a semiconductor device in which a multistage amplifier unit is built.
It is another object of the present invention to provide a technique for forming a wire that connects an electrode of a semiconductor element to a bonding pad of a wiring accurately at a predetermined length in a semiconductor device in which a multistage amplifier unit is built.
It is still another object of the present invention to provide a technique for fixing the length of a wire that connects an electrode of a semiconductor element to a bonding pad of a wiring accurately at a predetermined length and fixing the parasitic inductance in a semiconductor device in which a multistage amplifier unit is built, thereby stabilizing the production yield of semiconductor devices.
It is still another object of the present invention to reduce the variation of the parasitic inductance at the output terminal side of the transistor in the final stage of a semiconductor device in which a multistage amplifier is built.
It is still another object of the present invention to improve the output of a semiconductor device (high frequency power amplification unit) in which a multistage amplifier unit is built and improve the output of a radio communication device in which the high frequency power amplification unit is built.
These and other objects, novel features of the present invention will become more apparent upon reading of the following detailed description and accompanying drawings.